To prevent a malfunction of a semiconductor device including a shift register by providing a transistor capable of suppressing negative direction shift (minus shift) of threshold voltage.
As a charging circuit for charging a gate node (node N1) of a transistor Q1 which pulls up an output terminal OUT of a unit shift register, a dual gate transistor Q3D comprised of two transistors serially connected between a first power supply terminal S1 and the node N1 is used. The dual gate transistor Q3D is constituted so that a connection node (node N3) between the two transistors constituting the dual gate transistor Q3D is reduced to an L level according to variation of a gate from an H level to an L level by capacity coupling between the gate and the node N3.
HIDA YOICHI
MURAI HIROYUKI
MORI SEIICHIRO
| JP2006107692A | 2006-04-20 | |||
| JPS58188396A | 1983-11-02 | |||
| JP2003101406A | 2003-04-04 | |||
| JP2005251335A | 2005-09-15 |
Takahiro Arita
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