Title:
SEMICONDUCTOR DEVICE, SUBSTRATE INCLUDING THE SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE ON SUBSTRATE (CMOS DEVICE ADAPTED SO AS TO REDUCE LATCHUP, AND METHOD OF MANUFACTURING THE SAME)
Document Type and Number:
Japanese Patent JP2007201463
Kind Code:
A
Abstract:
To provide a semiconductor device adapted to reduce latchups.
The semiconductor device includes (1) a shallow-trench-isolation (STI) oxide region; (2) a first metal-oxide-semiconductor field-effect transistor (MOSFET) coupled to a first side of the STI oxide region; (3) a second MOSFET coupled to a second side of the STI oxide region, wherein the portions of the first and second MOSFETs are coupled into a loop to form first and second bipolar junction transistors (BJTs); and (4) a dopant-implanted region, formed below the STI oxide region, where the dopant-implanted region forms a portion of the BJT loop and is adapted to reduce a gain of the loop.
COPYRIGHT: (C)2007,JPO&INPIT
Inventors:
CHARLES WILLIAM KOBURGER III
FURUKAWA TOSHIHARU
MANDELMAN JACK ALLAN
FURUKAWA TOSHIHARU
MANDELMAN JACK ALLAN
Application Number:
JP2007009439A
Publication Date:
August 09, 2007
Filing Date:
January 18, 2007
Export Citation:
Assignee:
IBM
International Classes:
H01L21/265; H01L27/08; H01L21/76; H01L21/8238; H01L27/092
Attorney, Agent or Firm:
Takeshi Ueno
Tasaichi Tanae
Yoshihiro City
Hiroshi Sakaguchi
Tasaichi Tanae
Yoshihiro City
Hiroshi Sakaguchi
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