To provide a semiconductor device for clock generator, a system board, and a multi-phase clock generating circuit in which stable operations of a circuit is made possible and an output clock signal of a uniform duty ratio is obtained by generating a clock signal with a frequency-divided output smaller than or equal to a decimal point of an oscillation frequency of a VCO.
In a PC mother board, a clock generator 1 has a PLL circuit 14 with a VCO 13 incorporated therein, a plurality of frequency divider circuits 15a-15i for outputting a plurality of clock signals of 1/N frequency division with an output frequency of the PLL circuit 14 as a reference to make possible at least one frequency-divided output smaller than or equal with the decimal point, and clock selector circuits 16a-16d for selecting any one of frequency-divided outputs outputted from the frequency divider circuits 15a-15i and outputting the clock signal of the selected frequency dividing ratio, and the clock signal is generated in every unit of a 0.5 divided-frequency, for example, in the oscillation frequency of the VCO 13.
YONETANI HIROYUKI
TAKAGI KOJI
NAKANO KENICHI
HITACHI ULSI SYS CO LTD
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