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Title:
SEMICONDUCTOR DEVICE AND TEST METHOD THEREOF
Document Type and Number:
Japanese Patent JP2011181174
Kind Code:
A
Abstract:

To provide a semiconductor device and a test method thereof, for achieving a high-speed test at a desired operating frequency.

An SiP 101 includes a logic chip 103A and a memory chip 103B. The memory chip 103B includes a memory circuit to be tested.The logic chip 103A includes an internal logic circuit 20 and a test processing circuit 21 electrically connected thereto. The test processing circuit 21 is connected with an access terminal of the memory circuit to test the memory circuit by supplying a test signal input from an external terminal 23n. The test processing circuit 21 has a high-speed test control circuit for adjusting a signal delay, and supplies in the high-speed test at an actual operating speed, the test signal supplied from the external terminal 23n to the access terminal through the high-speed test control circuit.


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Inventors:
HATTORI TAKASHI
HASHIZUME YUMIKO
NISHINO TATSUHIRO
IKEDA KOJI
Application Number:
JP2011097011A
Publication Date:
September 15, 2011
Filing Date:
April 25, 2011
Export Citation:
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Assignee:
RENESAS ELECTRONICS CORP
International Classes:
G11C29/12; G01R31/28; G11C29/02
Domestic Patent References:
JPH09311160A1997-12-02
JPH0676566A1994-03-18
JP2004158098A2004-06-03
JP2002329395A2002-11-15
JP2003077296A2003-03-14
JP2000111618A2000-04-21
JP4949707B22012-06-13
Attorney, Agent or Firm:
Ken Ieiri



 
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