Title:
SEMICONDUCTOR DEVICE TEST SYSTEM
Document Type and Number:
Japanese Patent JP3553522
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To shorten processing time by simultaneously measuring harmonics to the n-th harmonics.
SOLUTION: In the case of measuring the harmonics of a semiconductor device DUT, a contact of a switching means 10 is controlled in such a way as to switch to the side of a frequency multiplication mixing means 11 by a control signal from a processing device 2. A signal LO from an LO signal source 9 and a signal RF from the semiconductor device DUT are inputted to the frequency multiplication mixing means 11. The frequency multiplication mixing means 11 performs addition and subtraction on n-times the signal LO and a signal RF, and outputs an obtained value as an intermediate frequency signal IF. Only low frequencies of the signal IF are passed by an LPF and inputted to a transmitter tester 5. The transmitter tester 5 converts the signal IF into digital data and performs FFT analysis on the converted digital data. By this, a harmonic component is isolated to analyze frequencies and levels.
Inventors:
Toshiyuki Takahashi
Application Number:
JP2001143416A
Publication Date:
August 11, 2004
Filing Date:
May 14, 2001
Export Citation:
Assignee:
Anritsu Co., Ltd.
International Classes:
G01R23/16; G01R31/28; G01R31/316; G01R31/3183; G01R27/28; (IPC1-7): G01R27/28; G01R23/16; G01R31/28; G01R31/316; G01R31/3183
Domestic Patent References:
| JP11174099A |
Attorney, Agent or Firm:
Norimitsu Nishimura
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