Title:
フィン型FETを有する半導体装置およびその製造方法
Document Type and Number:
Japanese Patent JP5291736
Kind Code:
B2
Abstract:
A method includes forming a first fin and a second fin extending above a semiconductor substrate, with a shallow trench isolation (STI) region between them. A space is defined between the first and second fins above a top surface of the STI region. A first height is defined between the top surface of the STI region and top surfaces of the first and second fins. A flowable dielectric material is deposited into the space. The dielectric material has a top surface above the top surface of the STI region, so as to define a second height between the top surface of the dielectric material and the top surfaces of the first and second fins. The second height is less than the first height. First and second fin extensions are epitaxially formed above the dielectric, on the first and second fins, respectively, after the depositing step.
Inventors:
Chen Hongkai
Hayashi Kenshin
Hayashi Akira
Sen
Peng Yuanqing
Hayashi Kenshin
Hayashi Akira
Sen
Peng Yuanqing
Application Number:
JP2011042416A
Publication Date:
September 18, 2013
Filing Date:
February 28, 2011
Export Citation:
Assignee:
Taiwan Semiconductor Manufacturing Company,Ltd.
International Classes:
H01L21/8238; H01L21/20; H01L21/205; H01L21/316; H01L21/318; H01L21/336; H01L27/092; H01L29/78
Domestic Patent References:
| JP2009267021A | ||||
| JP2007165780A | ||||
| JP2009032955A | ||||
| JP2011101002A | ||||
| JP2009054705A |
Attorney, Agent or Firm:
Kawamura Taku
Yousuke Fujimori
Seiji Tani
Yousuke Fujimori
Seiji Tani
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