Title:
SEMICONDUCTOR DEVICE WITH MULTILAYERED WIRING
Document Type and Number:
Japanese Patent JP2007012773
Kind Code:
A
Abstract:
To provide a semiconductor device with a structure capable of preventing disconnection caused by wiring recession occurring on fine wiring of 0.1 μm or less connected through vias.
An insulating film 204 is formed on a silicon substrate 203, and M1 wiring 103 and M2 wiring 104 are alternately disposed in this region, and the wiring is connected through vias 105. Wiring widths of the M1 wiring 103 and the M2 wiring 104 are 70 nm and the same with each other to be the minimum wiring width. In this structure, the via 105 has the same minimum width as those of the M1 wiring 103 and the M2 wiring 104, and the M1 wiring 103 and the M2 wiring 104 are commonly connected through a plurality of the vias 105.
Inventors:
MATSUBARA YOSHIHISA
Application Number:
JP2005189847A
Publication Date:
January 18, 2007
Filing Date:
June 29, 2005
Export Citation:
Assignee:
NEC ELECTRONICS CORP
International Classes:
H01L21/66; H01L21/3205; H01L21/768; H01L23/52
Attorney, Agent or Firm:
Akio Miyazaki
Ishibashi Masayuki
Masaaki Ogata
Ishibashi Masayuki
Masaaki Ogata
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