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Title:
SEMICONDUCTOR DEVICE WITH TEST CIRCUIT
Document Type and Number:
Japanese Patent JPH01266736
Kind Code:
A
Abstract:

PURPOSE: To check specifications of the title semiconductor device such as an operating speed by easily finding a gate having any process failure by switching on and off test input and normal input switches based upon a control signal fed from a control line and changing the operation to a test mode.

CONSTITUTION: A basic single gate of a gate array comprises a two-input NAND gate 11 for example, which includes on one input side a test MOS transistor 12 and a normal input [1] MOS transistor 13 while including on the other input side a test MOS transistor 14 and a normal input [2] MOS transistor 15. The transistors 12, 14 are connected to a control line 1 while the transistors 13, 15 are connected to a control line 2. A given control signal is applied to the control lines 1, 2 to switch on and off transistors 12 to 15. Hereby, a gate having any process failure can easily be found to also check specifications such as an operating speed.


Inventors:
MATSUMOTO ISAO
SHIMAUCHI YUKI
Application Number:
JP9443688A
Publication Date:
October 24, 1989
Filing Date:
April 19, 1988
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H01L21/66; H01L21/82; G01R31/28; (IPC1-7): G01R31/28; H01L21/66; H01L21/82
Domestic Patent References:
JPS59111343A1984-06-27
JPS60154637A1985-08-14
Attorney, Agent or Firm:
Yoshiyuki Osuge (1 outside)