To utilize a plurality of semiconductor devices whose operation modes are controlled by the logic of an operation mode setting signal group to expand the address space.

The semiconductor device is provided with a plurality of SRAM chips 1 of a DDR(double data rate) specification, a bank control circuit 3 and a CQ control circuit 4. There is no possibility that synchronous clocks outputted from semiconductor devices respectively belonging to different groups collide with each other in a timing manner because only synchronous clocks outputted by semiconductor devices of groups that output valid data are selected and outputted at the time of outputting synchronous clocks (e.g. SRAM echo clock of DDR specification) synchronized with a data output.