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Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP2002217706
Kind Code:
A
Abstract:

To provide a semiconductor device that eliminates the occurrence of an erroneous comparison result just after power-down control in programmable impedance control circuit so as to attain the power-down control by a stop clock.

In the semiconductor device that has a connection terminal to which an external resistor is connected, an output buffer having transistor(TR) group for external drive where TRs with different widths are connected in parallel, an output impedance control means that automatically adjusts the impedance of the output buffer depending on the resistance of the external resistor, and a power-down function, the output impedance control means has a dummy buffer similarly configured to the output buffer and a comparison means that compares a 1st current flowing through the connection terminal with a 2nd current flowing through the dummy buffer and controls the comparison means to be inoperative for a recovery period of the dummy buffer after the power-down function is released.


Inventors:
HATADA HIROSHI
OTSUKA NOBUAKI
Application Number:
JP2001007681A
Publication Date:
August 02, 2002
Filing Date:
January 16, 2001
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
G11C11/413; G11C11/407; G11C11/409; G11C11/417; H03K19/0175; (IPC1-7): H03K19/0175; G11C11/407; G11C11/409; G11C11/413; G11C11/417
Attorney, Agent or Firm:
Hidekazu Miyoshi (7 outside)



 
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