Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP2007242660
Kind Code:
A
Abstract:
To obtain a semiconductor device having a resistive element formed in the SOI layer of an SOI substrate to minimize the impact of leakage.
An n+diffusion region 11 is formed selectively in an SOI layer 3, and a perfect isolation region 4 is formed to cover the entire peripheral region of the n+diffusion region 11. Since the perfect isolation region 4 penetrates the SOI layer 3 to reach a buried oxide film 2, the n+diffusion region 11 is electrically isolated completely from the outside by the perfect isolation region 4. The n+diffusion region 11 extends in the longitudinal direction on the drawing, and is formed to have a longitudinally elongated rectangular plan view. A silicide film 6a is formed in the surface on one end side of the n+diffusion region 11, a silicide film 6b is formed in the surface on the other end side, and metal plugs 7 and 7 are formed on the silicide films 6a and 6b, respectively.
COPYRIGHT: (C)2007,JPO&INPIT
Inventors:
KOMATSU HIROSHI
Application Number:
JP2006058954A
Publication Date:
September 20, 2007
Filing Date:
March 06, 2006
Assignee:
RENESAS TECH CORP
International Classes:
H01L21/822; H01L21/02; H01L21/76; H01L21/762; H01L21/8234; H01L27/04; H01L27/06; H01L27/08; H01L27/12; H01L29/786
Domestic Patent References:
| JP2003060044A | 2003-02-28 | | | |
| JPH0467666A | 1992-03-03 | | | |
| JP2001144254A | 2001-05-25 | | | |
| JP2002246600A | 2002-08-30 | | | |
| JPH02250315A | 1990-10-08 | | | |
| JP2003092360A | 2003-03-28 | | | |
| JP2000340674A | 2000-12-08 | | | |
Attorney, Agent or Firm:
Shigeaki Yoshida
Yoshitake Hidetoshi
Takahiro Arita
