Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP2008028111
Kind Code:
A
Abstract:
To provide technique for arranging multiple elements in a limited TEG region in a semiconductor device.
The semiconductor device includes: a MOS transistor 102a, a MOS transistor 102b, a pad 101d connected to the sources of the MOS transistors 102a, 102b, a pad 101e connected to the drain of the MOS transistor 102a, and a pad 101c connected to the drain of the MOS transistor 102b. The pad 101e is formed of first metal (M1), and the pad 101c is of second metal (M2) on the upper layer of the first metal. The pads 101e, 101c are arranged by superimposition via an insulating film. The MOS transistor 102a is measured by using the pads 101d, 101e, and the MOS transistor 102b is by using the pads 101d, 101c.
Inventors:
FUJISHIMA KENJI
WATANABE AKIO
YOSHIDA HIROSHI
WATANABE AKIO
YOSHIDA HIROSHI
Application Number:
JP2006198411A
Publication Date:
February 07, 2008
Filing Date:
July 20, 2006
Export Citation:
Assignee:
RENESAS TECH CORP
International Classes:
H01L21/66; G01R31/26; H01L21/822; H01L27/04
Attorney, Agent or Firm:
Yamato Tsutsui
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