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Patent Searching and Data


Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP2009239302
Kind Code:
A
Abstract:

To provide a technique capable of improving the planarity of a surface of a member which is embeddedin a plurality of recessed portions, without causing increase in the production time.

A first dummy pattern DP1 of relatively large area and a second dummy pattern DP2 of relatively small area are arranged in a dummy area FA, to form the dummy pattern up to the vicinity of the boundary BL between a device forming area DA and the dummy area FA. Thereby, the planarity of the surface of a silicon oxide film embedded in isolation trenches can be improved in the entire area of the dummy area FA. Furthermore, the relatively large areas of the dummy area FA are occupied with the first dummy pattern DP1 to suppress the increase in data amount of a mask.


Inventors:
Kuroda, Kenichi
Watabe, Kozo
Yamamoto, Hirohiko
Application Number:
JP2009000162579
Publication Date:
October 15, 2009
Filing Date:
July 09, 2009
Export Citation:
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Assignee:
RENESAS TECHNOLOGY CORP
International Classes:
H01L21/76; H01L21/3205; H01L21/822; H01L23/52; H01L27/04; H01L21/70; H01L21/02; H01L23/52; H01L27/04