To provide a semiconductor device typified by a display device having more excellent display quality, in which parasitic resistance generated in a connection portion between a semiconductor layer and an electrode is suppressed and adverse effects such as voltage drop, a defect in signal writing to a pixel, a defect in grayscale, and the like due to wiring resistance are prevented.
The semiconductor device may have a structure where a wiring with low resistance is connected to a thin-film transistor in which a source electrode and a drain electrode that include metal with high oxygen affinity are connected to an oxide semiconductor layer with a suppressed impurity concentration. In addition, the thin-film transistor using the oxide semiconductor may be surrounded by insulating films to be sealed.
KOYAMA JUN
TAKAHASHI MASAHIRO
KISHIDA HIDEYUKI
MIYANAGA SHOJI
NAKAMURA YASUO
SUGAO ATSUHEI
UOJI HIDEKI
JP2007123861A | 2007-05-17 | |||
JP2006165520A | 2006-06-22 | |||
JP2008219008A | 2008-09-18 | |||
JP2009231664A | 2009-10-08 |
Next Patent: METHOD OF REMOVING HEAVY METAL IN SEMICONDUCTOR SUBSTRATE