Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP2013191256
Kind Code:
A
Abstract:
To provide a semiconductor device including a plurality of resistance-change memory cells, which can prevent excessive peak current when a potential of a commonly used source line is changed in a case where the source line is commonly used to reduce a layout size.
The semiconductor device has: a plurality of bit lines respectively connected to one ends of the plurality of resistance-change memory cells; a common source line commonly connected to the other ends of the plurality of resistance-change memory cells; and a source line driver controlling the potential of the common source line. The source line driver variably controls current supplied to the common source line.
Inventors:
NAKAI KIYOSHI
Application Number:
JP2012057126A
Publication Date:
September 26, 2013
Filing Date:
March 14, 2012
Export Citation:
Assignee:
ELPIDA MEMORY INC
International Classes:
G11C13/00
Attorney, Agent or Firm:
Kato Asamichi