To provide a semiconductor device having a layout capable of reducing the area of a sense amplifier region by efficiently arranging transistors of a sense amplifier circuit.
A semiconductor device includes: a first bit line extending in a first direction; a second bit line extending in the first direction; a power-supply line; and a sense amplifier circuit having a first transistor that includes a first gate electrode connected to the first bit line, a first diffusion region connected to the second bit line, a second diffusion region connected to the power-supply line, and a first channel provided between the first diffusion region and the second diffusion region, and a second transistor that includes a second gate electrode connected to the second bit line, a third diffusion region connected to the first bit line, a fourth diffusion region connected to the power-supply line, and a second channel provided between the third diffusion region and the fourth diffusion region. The channel widths of the first channel and the second channel extend in a second direction orthogonal to the first direction.
Kiuchi Uchida
Mitsuru Aoki
Next Patent: TAPPED COIL AND MANUFACTURING METHOD THEREFOR