Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP2014139856
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To suppress deterioration of transistors.SOLUTION: An embodiment of the invention includes a first period and a second period. In the first period, a first transistor and a second transistor are alternately and repeatedly turned on and off, and a third transistor and a fourth transistor are turned off. In the second period, the first transistor and the second transistor are turned off and the third transistor and the fourth transistor are alternately and repeatedly turned on and off. Thus, since the period during which the transistors are turned on can be shortened, characteristics degradation of the transistors is suppressed.
Inventors:
KIMURA HAJIME
UMEZAKI ATSUSHI
UMEZAKI ATSUSHI
Application Number:
JP2014021896A
Publication Date:
July 31, 2014
Filing Date:
February 07, 2014
Export Citation:
Assignee:
SEMICONDUCTOR ENERGY LAB
International Classes:
G11C19/28; G09G3/20; G09G3/36; G11C19/00; H03K3/356; H03K23/44
Domestic Patent References:
| JP2007250052A | 2007-09-27 | |||
| JP2008130139A | 2008-06-05 | |||
| JP2011181122A | 2011-09-15 | |||
| JP2006189762A | 2006-07-20 | |||
| JP2007151092A | 2007-06-14 | |||
| JP2008097774A | 2008-04-24 | |||
| JP2010152347A | 2010-07-08 |
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