Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP2015029148
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To provide a multi-port SRAM cell, which is a semiconductor device, capable of reducing access time.SOLUTION: Regarding a P well region and an N well region in which a pair of CMOS inverters constituting a multiport SRAM cell are formed, the P well region is divided into two P well regions PW1 and PW2, and the PW1 and PW2 are formed on both sides of the N well region NW so that the boundaries between the regions are parallel to a bit line. A pair of access gates N3 and N5 and a pair of access gates N4 and N6 are each formed in the divided two P well regions so that the length of a bit line is shortened and the wiring capacity is reduced.
Inventors:
ARAI KOJI
MIYANISHI ATSUSHI
MIYANISHI ATSUSHI
Application Number:
JP2014213120A
Publication Date:
February 12, 2015
Filing Date:
October 17, 2014
Export Citation:
Assignee:
RENESAS ELECTRONICS CORP
International Classes:
H01L21/8244; H01L27/11
Domestic Patent References:
| JPH10178110A | 1998-06-30 | |||
| JPH077089A | 1995-01-10 | |||
| JPH04238191A | 1992-08-26 | |||
| JP2000133724A | 2000-05-12 | |||
| JPH10178110A | 1998-06-30 | |||
| JPH077089A | 1995-01-10 | |||
| JPH04238191A | 1992-08-26 | |||
| JP2000133724A | 2000-05-12 | |||
| JPH0922987A | 1997-01-21 | |||
| JPH06342892A | 1994-12-13 | |||
| JPH0697393A | 1994-04-08 |
Attorney, Agent or Firm:
Hiroaki Sakai