Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP2015179205
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To provide a highly reliable semiconductor device which can prevent wiring delay inside a semiconductor chip and reduce power consumption by minimizing a problematic clock skew caused by wiring delay and avoiding the insertion of a number of buffer cells for clock skew control.SOLUTION: A semiconductor device comprises: a semiconductor layer 11 having a light receiving element 22 and a functional element 23; an electric wiring layer 12 formed on a principal surface of the semiconductor layer 11 and having an electrical wiring 12A connecting between the light receiving element 22 and the functional element 23; a first optical wiring layer 13a formed on a principal surface of the electric wiring layer 12; and a second optical wiring layer 13b which is connected to the first optical wiring layer 13a and extends in a perpendicular direction relative to the principal surface of the electric wiring layer 12 and is connected to the receiving element 22.
Inventors:
SASAKI KOICHI
Application Number:
JP2014056862A
Publication Date:
October 08, 2015
Filing Date:
March 19, 2014
Export Citation:
Assignee:
CANON KK
International Classes:
G02B6/122; G02B6/42; H01L27/15; H01L31/0232; H01S5/02; H01S5/026
Domestic Patent References:
| JP2008090074A | 2008-04-17 | |||
| JP2001237411A | 2001-08-31 | |||
| JP2006126369A | 2006-05-18 | |||
| JP2011017787A | 2011-01-27 |
Foreign References:
| US5268973A | 1993-12-07 |
Attorney, Agent or Firm:
Takayoshi Kokubun
Previous Patent: HARD COAT FILM, POLARIZING PLATE, AND IMAGE DISPLAY DEVICE
Next Patent: LENS BARREL AND ELECTRONIC DEVICE
Next Patent: LENS BARREL AND ELECTRONIC DEVICE