Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP2022045697
Kind Code:
A
Abstract:
To provide a semiconductor device in which damage of a wiring layer can be suppressed.SOLUTION: A semiconductor device includes: a pad section; a protection circuit arranged at a position separated from the pad section in a plan view; N pieces of wiring layers; and a plurality of conductive vias connecting respective wiring layers adjacent in a lamination direction. The semiconductor device further includes, in a plan view, a first area, a second area, and a third area connecting the first and the second areas. The N pieces of wiring layers are arranged ranging over the first, second, and third areas. A first wiring layer on a pad section side is connected to the pad section in the first area. An N-th wiring layer on a protection circuit side is connected to the protection circuit in the second area. In the second area and the third area, when a total cross-sectional area of an i-th conductive via for connecting an i-th wiring layer located at an i-th position from a top of the N pieces of wiring layers and an (i+1)-th wiring layer located at an (i+1)-th position is represented as Si, S1 is smaller than any of Sj.SELECTED DRAWING: Figure 4
Inventors:
TANAKA HIDETOSHI
TSUKAMOTO MAI
TSUKAMOTO MAI
Application Number:
JP2020151424A
Publication Date:
March 22, 2022
Filing Date:
September 09, 2020
Export Citation:
Assignee:
SOCIONEXT INC
International Classes:
H01L21/822; H01L21/3205; H01L21/82; H01L21/8238; H01L27/06
Attorney, Agent or Firm:
Tadashige Ito
Tadahiko Ito
Tadahiko Ito