Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP3430920
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a semiconductor device for reducing as much output capacity as possible in an SOI(silicon-on insulator)-LDMOSFET(lateral double diffused MOSFET) having a drain pad formed at a center in a surface structure.
SOLUTION: An SOI-LDMOSFET 101 has a laced track structure in a surface manner and so-called a pectinated structure having a protrusion and recess structure in a surface structure. A part of a drain region 107 is deleted. Ap-type well region 106 formed to arrive at an insulating layer from a surface is intruded into the deleted region 114 isolated from the region 107.
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Inventors:
Hayasaki Kajo
Masahiko Suzumura
Yuji Suzuki
Yoshifumi Shirai
Takashi Kishida
▲高▼野 仁路
Takeshi Yoshida
Masahiko Suzumura
Yuji Suzuki
Yoshifumi Shirai
Takashi Kishida
▲高▼野 仁路
Takeshi Yoshida
Application Number:
JP14458298A
Publication Date:
July 28, 2003
Filing Date:
May 26, 1998
Export Citation:
Assignee:
MATSUSHITA ELECTRIC WORKS,LTD.
International Classes:
H01L29/78; H01L29/786; (IPC1-7): H01L29/786; H01L29/78
Attorney, Agent or Firm:
Keisei Nishikawa (1 person outside)
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