Title:
半導体装置
Document Type and Number:
Japanese Patent JP3626452
Kind Code:
B2
Abstract:
An output buffer circuit including a programmable impedance buffer configured to match a buffer size thereof with an external impedance, a buffer size decision circuit configured to generate a plurality of buffer size signals for determining the buffer size of the programmable impedance buffer synchronized with a first clock signal, and an impedance adjustment circuit configured to adjust the buffer size based on the buffer size signals in response to a level of an output data signal.
Inventors:
Keiichi Kushida
Application Number:
JP2001395749A
Publication Date:
March 09, 2005
Filing Date:
December 27, 2001
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
G11C11/409; H01L21/822; H01L27/04; H03K19/00; H03K19/0175; (IPC1-7): H03K19/0175; G11C11/409; H01L21/822; H01L27/04
Domestic Patent References:
| JP11027132A | ||||
| JP10041803A | ||||
| JP11031960A | ||||
| JP11340810A |
Attorney, Agent or Firm:
Hideaki Togawa