Title:
半導体装置
Document Type and Number:
Japanese Patent JP4088120
Kind Code:
B2
Abstract:
It is intended to prevent a crack from occurring in a circuit region during dicing, while preventing oxidation and corrosion of a seal ring including a layer of copper as the uppermost layer thereof. A passivation film (120) has an opening (123) formed therein, The opening (123) is formed so as to reach an interlayer insulating film (109) and disposed so as to surround a periphery of a seal ring (110). As a result, a top face of a second interconnect layer (114) is completely covered by the passivation film (120), and is not exposed to an ambient air. Hence, it is possible to prevent an effect of protecting a semiconductor device achieved by the seal ring (110) from being reduced due to oxidation and corrosion of the second interconnect layer (114). Further, provision of the opening (123) does not allow a stress generated at a time of cutting a dicing region during dicing to easily propagate to a portion of the passivation film (120) present on the circuit region. This prevents occurrence of a crack in the circuit region.
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Inventors:
Kazuro Tomita
Application Number:
JP2002234387A
Publication Date:
May 21, 2008
Filing Date:
August 12, 2002
Export Citation:
Assignee:
Renesas Technology Corp.
International Classes:
H01L21/3205; H01L21/78; H01L23/52; H01L23/00; H01L23/31
Domestic Patent References:
| JP9045766A | ||||
| JP2001267325A |
Attorney, Agent or Firm:
Yoshitake Hidetoshi
Takahiro Arita
Takahiro Arita