Title:
半導体装置
Document Type and Number:
Japanese Patent JP4094984
Kind Code:
B2
Abstract:
An HNMOS transistor ( 4 ) has its drain electrode connected to the gate electrode of an NMOS transistor ( 21 ), and a logic circuit voltage (VCC) is applied to the drain electrode of the NMOS transistor ( 21 ) through a resistor ( 32 ). A ground potential is applied to the source electrode of the NMOS transistor ( 21 ). A drain potential (V 2 ) at the NMOS transistor ( 21 ) is monitored by an interface circuit ( 1 ), for indirectly monitoring a potential (VS). Thus provided is a high voltage integrated circuit for preventing damage to a semiconductor device used for performing bridge rectification of a power line.
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Inventors:
Kazuhiro Shimizu
Application Number:
JP2003119641A
Publication Date:
June 04, 2008
Filing Date:
April 24, 2003
Export Citation:
Assignee:
Mitsubishi Electric Corporation
International Classes:
H01L21/8234; H03K17/08; H01L21/8238; H01L27/088; H01L27/092; H03K17/06; H03K17/56; H03K17/687; H03K19/00
Domestic Patent References:
| JP2003101391A | ||||
| JP2003032102A | ||||
| JP2002204581A | ||||
| JP11112313A | ||||
| JP10341578A | ||||
| JP10056782A | ||||
| JP9182463A | ||||
| JP9219976A | ||||
| JP7297698A |
Attorney, Agent or Firm:
Shigeaki Yoshida
Yoshitake Hidetoshi
Takahiro Arita
Yoshitake Hidetoshi
Takahiro Arita