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Title:
半導体装置
Document Type and Number:
Japanese Patent JP4302354
Kind Code:
B2
Abstract:

To reduce development cost of a test program for a memory chip mounted on a semiconductor device.

An access signal generation circuit formed in a chip and to be mounted on a semiconductor device converts an external signal to a memory access signal in accordance with an interface of a first memory chip. A first selection circuit selects the external signal and the memory access signal at active time and inactive time of a test start signal respectively, and the selected signal is output to the first memory chip. Specifically, the first memory chip can be directly accessed from the outside through selection of the external signal by the first selection circuit at a test mode. Therefore, the test program for testing a simple body of the first memory chip can be utilized as a test program for the semiconductor device after assembly. Consequently, the test cost required for the program development or the like can be reduced.

COPYRIGHT: (C)2003,JPO


Inventors:
Toshikazu Nakamura
Satoshi Eto
Toshiya Midai
Ayako Sato
Takayuki Yoneda
Noriko Kawamura
Application Number:
JP2002018455A
Publication Date:
July 22, 2009
Filing Date:
January 28, 2002
Export Citation:
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Assignee:
Fujitsu Microelectronics Limited
International Classes:
G01R31/28; G06F12/16; G11C29/02; G11C29/00; H03K17/693
Domestic Patent References:
JP11017130A
JP4099977A
JP60171735A
JP2000268600A
JP4002000A
JP2186280A
JP4109500A
Attorney, Agent or Firm:
Furuya Fumio
Toshihide Mori



 
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