To reduce development cost of a test program for a memory chip mounted on a semiconductor device.
An access signal generation circuit formed in a chip and to be mounted on a semiconductor device converts an external signal to a memory access signal in accordance with an interface of a first memory chip. A first selection circuit selects the external signal and the memory access signal at active time and inactive time of a test start signal respectively, and the selected signal is output to the first memory chip. Specifically, the first memory chip can be directly accessed from the outside through selection of the external signal by the first selection circuit at a test mode. Therefore, the test program for testing a simple body of the first memory chip can be utilized as a test program for the semiconductor device after assembly. Consequently, the test cost required for the program development or the like can be reduced.
COPYRIGHT: (C)2003,JPO
JP2003006269 | LOGICAL SIMULATION METHOD |
JPH10319095 | SEMICONDUCTOR TESTING DEVICE |
WO/2009/006175 | TEST STRUCTURE, TEST STRUCTURE FORMATION AND MASK REUSE IN SEMICONDUCTOR PROCESSING |
Satoshi Eto
Toshiya Midai
Ayako Sato
Takayuki Yoneda
Noriko Kawamura
JP11017130A | ||||
JP4099977A | ||||
JP60171735A | ||||
JP2000268600A | ||||
JP4002000A | ||||
JP2186280A | ||||
JP4109500A |
Toshihide Mori