Title:
半導体装置
Document Type and Number:
Japanese Patent JP4529493
Kind Code:
B2
Abstract:
Memory blocks having memory cells which are comprised of vertical transistors and memory elements in which the resistance value is varied depending on the temperature imposed on the upper side thereof, are laminated to realize a highly-integrated non-volatile memory.
Inventors:
Kenichi Nagata
Kiyoshi Ito
Kiyoshi Ito
Application Number:
JP2004069985A
Publication Date:
August 25, 2010
Filing Date:
March 12, 2004
Export Citation:
Assignee:
株式会社日立製作所
International Classes:
H01L27/105; G11C7/00; H01L27/10; H01L27/115; H01L27/24; H01L45/00
Domestic Patent References:
| JP2003229537A |
Foreign References:
| WO2003065377A1 | ||||
| WO2003085675A1 |
Attorney, Agent or Firm:
Manabu Inoue