Title:
半導体装置
Document Type and Number:
Japanese Patent JP4571679
Kind Code:
B2
Abstract:
To provide a semiconductor apparatus improving the efficiency of the heat dissipation and suppressing the malfunction.
In the semiconductor apparatus 100, a laminated body of a memory chip 102 is provided on one surface of a wiring substrate, and an outer connecting terminal 112 is provided on the other surface of the wiring substrate. The semiconductor apparatus 100 includes: a first insulating layer 111 formed on the wiring substrate so as to seal the laminated body of the memory chip 102; and a heat dissipating post 113 in a region where the laminated chip 102 in the first insulating layer 111 is not formed.
COPYRIGHT: (C)2009,JPO&INPIT
More Like This:
| JPS5373364 | MULTILAYER PRINTED CIRCUIT BOARD |
Inventors:
Makoto Terui
Yasushi Shiraishi
Junji Tsuchimoto
Yasushi Shiraishi
Junji Tsuchimoto
Application Number:
JP2008009757A
Publication Date:
October 27, 2010
Filing Date:
January 18, 2008
Export Citation:
Assignee:
oki Semiconductor Co., Ltd.
International Classes:
H01L23/34; H01L23/12; H01L25/065; H01L25/07; H01L25/18
Domestic Patent References:
| JP2006210892A | ||||
| JP2006319243A | ||||
| JP2005244143A | ||||
| JP2006019340A | ||||
| JP2001291793A | ||||
| JP2007115760A | ||||
| JP2003124390A | ||||
| JP2000068423A | ||||
| JP2004356650A | ||||
| JP2004071961A | ||||
| JP2006269594A | ||||
| JP2004327624A | ||||
| JP2007150154A | ||||
| JP2005142312A |
Attorney, Agent or Firm:
Atsushi Nakajima
Kato Kazunori
Katsuichi Nishimoto
Hiroshi Fukuda
Kato Kazunori
Katsuichi Nishimoto
Hiroshi Fukuda