Title:
半導体装置
Document Type and Number:
Japanese Patent JP4711061
Kind Code:
B2
Abstract:
A semiconductor device including: a semiconductor layer; a gate insulating layer; a gate electrode; a channel region; a source region and a drain region; a guard ring region; an offset insulating layer; a first interlayer dielectric; a first shield layer formed above the first interlayer dielectric and the guard ring region and electrically connected to the guard ring region; a second interlayer dielectric; and a second shield layer formed above the second interlayer dielectric, wherein the first shield layer is provided outside of both ends of the gate electrode in a channel width direction when viewed from the top side; and wherein the second shield layer is provided in at least part of a first region and/or at least part of a second region, the first region being a region between one edge of the gate electrode and an edge of the first shield layer opposite to the edge of the gate electrode in the channel width direction when viewed from the top side, and the second region being a region between the other edge of the gate electrode and an edge of the first shield layer opposite to the other edge of the gate electrode in the channel width direction when viewed from the top side.
Inventors:
Masahiro Hayashi
Takasho Akiba
Kunio Watanabe
High Tomoro Ai
Kenmochi
Takasho Akiba
Kunio Watanabe
High Tomoro Ai
Kenmochi
Application Number:
JP2005265483A
Publication Date:
June 29, 2011
Filing Date:
September 13, 2005
Export Citation:
Assignee:
Seiko Epson Corporation
International Classes:
H01L29/78; H01L21/3205; H01L21/336; H01L21/761; H01L21/768; H01L21/822; H01L23/52; H01L23/522; H01L27/04
Domestic Patent References:
| JP2005116744A | ||||
| JP63038259A | ||||
| JP2002373896A | ||||
| JP49116990A | ||||
| JP56087344A |
Attorney, Agent or Firm:
Yukio Fuse
Mitsue Obuchi
Mitsue Obuchi