Title:
半導体装置
Document Type and Number:
Japanese Patent JP5007120
Kind Code:
B2
Abstract:
For example, one memory cell is configured using two memory cell transistors and one phase change element by disposing a plurality of diffusion layers in parallel to a bit-line, disposing gates between the diffusion layers so as to cross the bit-line, disposing bit-line contacts and source contacts alternately to the plurality of diffusion layers arranged in a bit-line direction for each diffusion layer, and providing a phase change element on the source contact. Also, the phase change element can be provided on the bit-line contact instead of the source contact. By this means, for example, increase in drivability of the memory cell transistors and reduction in area can be realized.
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Inventors:
Riichiro Takemura
Kenzo Kurochi
Takayuki Kawahara
Kenzo Kurochi
Takayuki Kawahara
Application Number:
JP2006513859A
Publication Date:
August 22, 2012
Filing Date:
May 19, 2005
Export Citation:
Assignee:
Renesas Electronics Corporation
International Classes:
H01L27/105; G11C13/00; G11C16/02; H01L27/10; H01L27/24; H01L45/00
Domestic Patent References:
| JP2004158578A | 2004-06-03 | |||
| JP2005071500A | 2005-03-17 | |||
| JP2004349504A | 2004-12-09 | |||
| JP2004127347A | 2004-04-22 | |||
| JP2003297069A | 2003-10-17 | |||
| JP2002540605A | 2002-11-26 | |||
| JP2004110867A | 2004-04-08 |
Foreign References:
| US20040085809A1 | 2004-05-06 |
Attorney, Agent or Firm:
Yamato Tsutsui