Title:
半導体装置
Document Type and Number:
Japanese Patent JP5695934
Kind Code:
B2
Abstract:
A semiconductor device including a non-volatile memory cell including a writing transistor which includes an oxide semiconductor, a reading transistor which includes a semiconductor material different from that of the writing transistor, and a capacitor is provided. Data is written or rewritten to the memory cell by turning on the writing transistor and supplying a potential to a node where a source electrode (or a drain electrode) of the writing transistor, one electrode of the capacitor, and a gate electrode of the reading transistor are electrically connected to each other, and then turning off the writing transistor so that the predetermined amount of charge is held in the node. Further, when a transistor whose threshold voltage is controlled and set to a positive voltage is used as the reading transistor, a reading potential is a positive potential.
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Inventors:
Shunpei Yamazaki
Jun Koyama
Kiyoshi Kato
Jun Koyama
Kiyoshi Kato
Application Number:
JP2011038201A
Publication Date:
April 08, 2015
Filing Date:
February 24, 2011
Export Citation:
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
International Classes:
H01L21/8242; H01L21/336; H01L21/8247; H01L27/108; H01L27/115; H01L29/786; H01L29/788; H01L29/792
Domestic Patent References:
| JP2002368226A | ||||
| JP2009277702A | ||||
| JP2004355691A | ||||
| JP7141882A | ||||
| JP63070558A | ||||
| JP2001230329A | ||||
| JP2001351386A | ||||
| JP2001053167A | ||||
| JP2009206508A |
Other References:
ウイリアムN.カー・ジャックP.マイズ,MOS/LSI設計と応用,日本,株式会社エレクトロニクスダイジェスト,1981年 5月10日,p.65-67