Title:
Semiconductor device
Document Type and Number:
Japanese Patent JP6128135
Kind Code:
B2
Abstract:
Provided is a semiconductor device in which an intermediate potential conductor plate faces a positive conductor plate and a negative conductor plate in order to reliably reduce inductance. The semiconductor device includes: an insulating substrate (11) on which at least four semiconductor elements forming a three-level power conversion circuit are mounted; a base plate (3) on which the insulating substrate is provided; a positive conductor plate (21) with a positive DC potential which is connected to one semiconductor element among the semiconductor elements; a negative conductor plate (22) with a negative DC potential which is connected to another semiconductor element among the semiconductor elements; and an intermediate potential conductor plate (23) with an intermediate potential which is connected to the remaining two semiconductor elements among the semiconductor elements. The positive conductor plate, the negative conductor plate, and the intermediate potential conductor plate are provided on the base plate. The positive conductor plate and the negative conductor plate are arranged close to the intermediate potential conductor plate so as to face the intermediate potential conductor plate.
Inventors:
Chen Sho Qing
Hiroaki Ichikawa
Hiroaki Ichikawa
Application Number:
JP2014560659A
Publication Date:
May 17, 2017
Filing Date:
January 10, 2014
Export Citation:
Assignee:
Fuji Electric Co., Ltd.
International Classes:
H02M7/48; H02M7/487
Domestic Patent References:
| JP2012110095A | ||||
| JP11089249A | ||||
| JP2011254672A | ||||
| JP4071303A | ||||
| JP2008252055A | ||||
| JP2002526023A |
Foreign References:
| WO2001031771A1 | ||||
| US20060274561 | ||||
| WO2012169521A1 |
Attorney, Agent or Firm:
Ichi Hirose
Hide Tanaka Tetsu
Hide Tanaka Tetsu
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