Title:
Semiconductor device
Document Type and Number:
Japanese Patent JP6219140
Kind Code:
B2
Abstract:
Provided is a semiconductor device having improved performance. A semiconductor substrate is formed with unit LDMOSFET elements. The unit LDMOSFET elements have respective source regions electrically coupled to each other via a first source interconnect line and a second source interconnect line. The unit LDMOSFET elements have respective gate electrodes electrically coupled to each other via a first gate interconnect line and also electrically coupled to a second gate interconnect line in the same layer as that of the second source interconnect line via the first gate interconnect line. The unit LDMOSFET elements have respective drain regions electrically coupled to a back surface electrode via a conductive plug embedded in a trench of the semiconductor substrate. Each of the first source interconnect line and the first gate interconnect line has a thickness smaller than that of the second source interconnect line. Over the plug, the first gate interconnect line extends.
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Inventors:
Yoshinori Yoshida
Koichi Kato
Tsuyoshi Kachi
Kagesuke Furuya
Koichi Kato
Tsuyoshi Kachi
Kagesuke Furuya
Application Number:
JP2013241987A
Publication Date:
October 25, 2017
Filing Date:
November 22, 2013
Export Citation:
Assignee:
Renesas Electronics Corporation
International Classes:
H01L21/8234; H01L21/3205; H01L21/336; H01L21/768; H01L21/822; H01L23/522; H01L25/07; H01L25/18; H01L27/04; H01L27/088; H01L29/06; H01L29/41; H01L29/417; H01L29/78
Domestic Patent References:
JP2002158353A | ||||
JP2003031805A | ||||
JP2009278028A | ||||
JP62150779A | ||||
JP2013093579A |
Attorney, Agent or Firm:
Yamato Tsutsui
Atsushi Sugada
Akiko Tsutsui
Tetsuya Sakaji
Atsushi Sugada
Akiko Tsutsui
Tetsuya Sakaji
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