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Title:
Semiconductor device
Document Type and Number:
Japanese Patent JP6249146
Kind Code:
B1
Abstract:
Ｓｉ基板（１）の上に窒化物半導体層（２，３，４）が設けられている。窒化物半導体層（２，３，４）の上にゲート電極（５）、ソース電極（６）及びドレイン電極（７）が設けられている。ドレイン電極（７）の下においてＳｉ基板（１）に、窒化物半導体層（２，３，４）と接するＰ型導電層（１１）が設けられている。

Inventors:
Toshiaki Kitano
Application Number:
JP2017545695A
Publication Date:
December 20, 2017
Filing Date:
April 28, 2017
Export Citation:
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Assignee:
Mitsubishi Electric Corporation
International Classes:
H01L21/338; H01L29/778; H01L29/812
Domestic Patent References:
JP2013038250A2013-02-21
JP2006196869A2006-07-27
JP2009009993A2009-01-15
JP2016509756A2016-03-31
JP2011204984A2011-10-13
JP2012248753A2012-12-13
Foreign References:
WO2011024440A12011-03-03
WO2014061254A12014-04-24
Attorney, Agent or Firm:
Mamoru Takada
Hideki Takahashi
Yoshimi Kuno



 
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