Title:
半導体装置
Document Type and Number:
Japanese Patent JP6541360
Kind Code:
B2
Abstract:
A low-power semiconductor device is provided. A memory device applicable to a multi-context programmable logic device (PLD) includes at least memory cells the number of which is the same as the number of contexts. Output nodes of the memory cells are electrically connected to an output node of a configuration memory through different path transistors. A circuit including a transistor and a capacitor makes a gate potential of the path transistor higher than a high-level potential. This prevents a decrease in the potential of the output node of the configuration memory due to the threshold voltage of the path transistor without an increase in power consumption.
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Inventors:
Ken Aoki
Uzumasa Munehiro
Uzumasa Munehiro
Application Number:
JP2015019838A
Publication Date:
July 10, 2019
Filing Date:
February 04, 2015
Export Citation:
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
International Classes:
H03K19/173; H01L21/82; H01L21/8234; H01L21/8242; H01L27/06; H01L27/088; H01L27/10; H01L27/108; H01L29/786
Domestic Patent References:
| JP2007122758A | ||||
| JP2013009306A | ||||
| JP2012257217A | ||||
| JP2009294508A | ||||
| JP2010225194A | ||||
| JP2013054346A | ||||
| JP2012065042A |
Foreign References:
| US20090146686 |