Title:
半導体装置
Document Type and Number:
Japanese Patent JP6890572
Kind Code:
B2
Abstract:
A nonvolatile semiconductor device which can be driven at low voltage is provided. A nonvolatile semiconductor device with low power consumption is provided. A Schmitt trigger NAND circuit and a Schmitt trigger inverter are included. Data is held in a period when the supply of power supply voltage is continued, and a potential corresponding to the data is stored at a node electrically connected to a capacitor before a period when the supply of power supply voltage is stopped. By utilizing a change in channel resistance of a transistor whose gate is connected to the node, the data is restored in response to the restart of the supply of power supply voltage.
Inventors:
Ken Aoki
Yoshimoto Kurokawa
Uzumasa Munehiro
Yoshimoto Kurokawa
Uzumasa Munehiro
Application Number:
JP2018222965A
Publication Date:
June 18, 2021
Filing Date:
November 29, 2018
Export Citation:
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
International Classes:
H03K19/00; G11C14/00; H01L21/822; H01L21/8234; H01L21/8238; H01L21/8239; H01L21/8244; H01L27/04; H01L27/088; H01L27/092; H01L27/105; H01L27/11; H01L27/1156; H01L29/786; H03K3/356
Domestic Patent References:
| JP2012217158A | ||||
| JP5110392A | ||||
| JP2013020691A | ||||
| JP2011171723A | ||||
| JP2000077982A | ||||
| JP2012009839A | ||||
| JP2009296123A |
Other References:
Niklas Lotze et al.,A 62 mV 0.13μm CMOS Standard-Cell-Based Design Technique Using Schmitt-Trigger Logic,IEEE Journal of Solid-State Circuits,2011年10月31日,Vol.47, No.1,p.47-60