半導体装置

Japanese Patent JP7065637

B2

There is to provide a semiconductor device capable of handling a signal having a voltage level of the low voltage power source stably. The semiconductor device includes first and second memory blocks having a plurality of memory transistors of storing data according to a level change of the threshold voltage and a plurality of memory gate lines of supplying each voltage to each gate of the memory transistors. The semiconductor device further includes first and second voltage control lines provided correspondingly to the first memory block, for driving the plural memory gate lines, and third and fourth voltage control lines provided correspondingly to the second memory block, for driving the plural memory gate lines. The semiconductor device further includes a first decoder of driving the first and the third voltage control lines, a second decoder of driving the second and the fourth voltage control lines, and a voltage control circuit of controlling a voltage to be supplied to the first and the second decoders. The voltage control circuit supplies a first voltage and a second voltage lower than the first voltage to the first decoder and supplies a third voltage between the first voltage and the second voltage and the second voltage to the second decoder, before the writing operation. The voltage control circuit supplies the first voltage and the third voltage to the first decoder and supplies a fourth voltage between the third voltage and the second voltage and a fifth voltage lower than the second voltage to the second decoder, in the writing operation mode.

Yoji Kashihara

JP2018030032A

May 12, 2022

February 22, 2018

Click for automatic bibliography generation  

Renesas Electronics Corporation

G11C16/08; G11C8/10; G11C16/04; H01L21/336; H01L27/11573; H01L29/788; H01L29/792

JP2016139449A
JP2019145979A
JP2019146021A

Fukami patent office

Previous Patent: Cool storage

Next Patent: Imidazole salt and its manufacturing method