PURPOSE: To increase the degree of pattern designing freedom and also to assure the working of a semiconductor device by setting a processing circuit between an asynchronous up-counter and a coincidence detecting circuit.

CONSTITUTION: The signal inputted from a pulse input terminal 8 is divided by a master-slave type dividing circuit 1 and an asynchronous up-counter circuit is formed with the serial arrangement of the divided signals. An exclusive OR 4 is used for the input processing of the master output and the value inputted from a set value input terminal 7 is inputted to the OR as a complement of 1 via an inverter. In this case, the output of the OR 4 serves as the master output of each circuit 1 and each signal has the extremely small possibility for occurrence of the hazard in terms of timing. Thus the pattern designing limitation is omitted and the pattern designing freedom is improved together with the stable designing actions.