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Patent Searching and Data


Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPH04170049
Kind Code:
A
Abstract:

PURPOSE: To attain desired delay by arranging dummy wiring which is not directly connected with a signal wiring and its in a potentially same phase or the reverse phase and that allows a stable selection.

CONSTITUTION: Logical circuits 1 and 3 decide one output respectively when input is determined. A potential generating circuit 4 is a circuit which gives potential to dummy wiring 5, and the output can be selected by a fuse and the potential of the dummy wiring 5 is decided by the positions of the selected fuses F1-F3. The dummy wiring 5 is in the dame phase as signal wiring 23 having the fixed potential decide by the position of the selected fuse. The decided potential difference between both wiring layers 6 and 7 is generated by forming dummy wiring layer 7 in insulating layer 9 on a semiconductor substrate 10, the charge quantity between the wiring layer 6 and 7 is varied and the signal wiring 2 is allowed to have signal delay. Thus, the most suitable delay time is attained.


Inventors:
MINAYAMA HARUMI
ISHIKAWA YUKIHIKO
Application Number:
JP29745990A
Publication Date:
June 17, 1992
Filing Date:
November 02, 1990
Export Citation:
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Assignee:
NIPPON ELECTRIC IC MICROCOMPUT
International Classes:
H01L23/52; G06F1/10; H01L21/3205; H01L21/82; H01L21/822; H01L27/04; (IPC1-7): H01L21/3205; H01L21/82; H01L27/04
Attorney, Agent or Firm:
Uchihara Shin