PURPOSE: To suppress the enlargement of chip area of dynamic RAM, etc., which is provided with a step-down circuit and stabilizes its operation while eliminating power source noise by providing a noise suppress circuit which necessitates small layout area and is resistant to the surge noise.

CONSTITUTION: A noise suppress circuit NS is provided between an outer power supply voltage supply terminal VCC of dynamic RAM, etc., provided with a step-down circuit and a earthing potential supply terminal VSS. The circuit NS consists of a P-channel MOSFETQ1 connected with an outer power supply voltage supply terminal for its source, a capacitor C1 that is provided between the MOSFETQ1 drain and the terminal VSS and is formed by using a gate capacity of the MOSFET, and at least three CMOS inverters N1-N3 that are provided in a serial manner between the terminal VCC and the MOSFETQ1 gate.