PURPOSE: To make a layout area for row decoder groups small by converting input signals having power supply potentials and ground potentials into potentials higher than the power supply potential and ground potentials without providing converting circuits.
CONSTITUTION: In a row decoder 810 a pull up circuit 811 is connected between a boost potential node 50c and a first node 812 and is provided with a p-channel MOS transistor 811a receiving a local resetting signal for a decoder RDPn at its gate electrode. A pull down circuit 813 is connected between the node 812 and a ground potential node 50b and is provided with n-channel MOS transistors 813a to 813d receiving row pre-decoding signals XA to XC and a subblock selecting signal BSn at their gate electrodes. Further, an output holding circuit 814 is driven by receiving a boosted voltage VPP and is provided with an inverter circuit 814b connected to nodes 812, 814a, 814c and a p-channel MOS transistor 814d connected to the boost potential 5Oc and nodes 814a, 814c.
TOMIUE KENJI
SAKAMI KAZUHIRO
IKEDA YUTAKA
INOUE YOSHINAGA
KAJIMOTO TAKESHI
MITSUBISHI ELECTRIC ENG