Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPH1041406
Kind Code:
A
Abstract:
To reduce the size by preventing the connecting position of a gate terminal and body terminal from being limited for a high speed operation owing to the connection of both terminals.
An n-type well layer NW is formed on a p-type bulk Si substrate PS and channel region PC is formed in this layer NW is composed of a semiconductor layer having the reverse polarity to the source and drain regions. A contact hole CHC is formed through a gate oxide film GO beneath the main body MP near the end EP of a gate electrode GT.
Inventors:
UEDA KIMIHIRO
Application Number:
JP18926896A
Publication Date:
February 13, 1998
Filing Date:
July 18, 1996
Export Citation:
Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
H01L21/8238; H01L21/84; H01L27/088; H01L27/092; H01L27/12; H01L29/10; H01L29/786; (IPC1-7): H01L21/8238; H01L27/092
Attorney, Agent or Firm:
Shigeaki Yoshida (2 outside)