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Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPH114155
Kind Code:
A
Abstract:

To reduce the noise of a power supply wire without impairing the high speed of an output buffer itself by connecting a first Nch transistor to a first Pch transistor in parallel between a voltage power source and an output terminal, and connecting a second Pch transistor to a second Nch transistor in parallel between a ground power source and an output terminal.

The sources of the Pch transistor P1 of an output driver and the Nch transistor N2 of the output driver are connected to a voltage power source VDD side, and drain is connected to OUTPAD1. The sources of the Pch transistor P2 of the output driver and the Nch transistor N1 of the output driver are connected to a ground power source VSS side, and the drain is connected to OUTPAD1. The charging/discharging of the additional capacity of the output terminal can be separated into two stages with such constitution and peak current can be suppressed. Thus, a stable operation for suppressing the noise of the power source line can be realized without impairing high speed.


Inventors:
ONO FUMIKO
KASHIMOTO HIROSHI
Application Number:
JP15407997A
Publication Date:
January 06, 1999
Filing Date:
June 11, 1997
Export Citation:
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Assignee:
SEIKO EPSON CORP
International Classes:
H03K19/003; H03K17/16; H03K17/687; H03K19/017; H03K19/0175; (IPC1-7): H03K19/0175; H03K17/16; H03K17/687; H03K19/003; H03K19/017
Attorney, Agent or Firm:
鈴木 喜三郎 (外2名)



 
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