Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS56104446
Kind Code:
A
Abstract:
PURPOSE:To securely isolate elements from each other by forming a semiconductor layer having a predetermined potential on the main surface of a semiconductor substrate, thereby preventing the formation of a channel. CONSTITUTION:MISFETs Q1, Q2 formed of impurity diffused layers and polycrystalline silicon gate electrodes 4 are provided, and an isolating conductor layer 8 is arranged through an insulating film (SiO2 film) 5 on the surface of the Si semiconductor substrate 1 of the isolating region I between the MISFETs Q1 and Q2. The layer 8 is formed of polycrystalline silicon formed in the same step as the step of forming the gate electrode 4, and connected to the substrate 1. Since the substrate 1 is grounded at the time of using, the layer 8 is also grounded, and no channel is induced on the surface of the substrate 1 just under the layer 8. Thus, the isolation can be securely performed, and the semiconductor device having high density can be formed.
Inventors:
INOUE TOSHIBUMI
KIHARA TOSHIMASA
KIHARA TOSHIMASA
Application Number:
JP569880A
Publication Date:
August 20, 1981
Filing Date:
January 23, 1980
Export Citation:
Assignee:
HITACHI LTD
International Classes:
H01L21/31; H01L21/76; H01L21/765; H01L21/8247; H01L27/118; H01L29/788; H01L29/792; (IPC1-7): H01L21/76; H01L21/95; H01L29/78
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