SEMICONDUCTOR DEVICE - CHO LSI GIJUTSU KENKYU KUMIAI

Title:

SEMICONDUCTOR DEVICE

Document Type and Number:

Japanese Patent JPS56118370

Kind Code:

A

Abstract:

PURPOSE: To form conductive layer with metals with higher melting point, smaller resistance and more excellent thermal properties, and to prevent stress on a substrate resulting from employment of such materials.

CONSTITUTION: When a gate electrode of an FET is made in a twofold structure of Mo and W, the possible stress on an Si substrate can be offset. If it is made in a single-fold Mo, tension stress occurs on the substrate. If it is made in a single-fold W, compression stress occurs. Therefore if made in the twofold structure of Mo and W the stresses offset each offer, and the possible deterioration in electrical properties to be caused by interface problems etc. and exfoliation can be prevented and a device with excellent resistance and thermal properties can be obtained. Order of stacking does not matter and employment of Mo-W alloy is equally effective.

More Like This:

WO/2003/098685	METHOD OF MAKING TRANSISTORS WITH GATE INSULATION LAYERS OF DIFFERING THICKNESS
JP2023553477	Method for manufacturing electronic semiconductor components and pretreated composite substrates for electronic semiconductor components
WO/2018/004632	A FINFET TRANSISTOR HAVING A TAPERED SUBFIN STRUCTURE

Inventors:

TADAMA NAOTAKE

Application Number:

JP2075680A

Publication Date:

September 17, 1981

Filing Date:

February 21, 1980

Export Citation:

Click for automatic bibliography generation Help

Assignee:

CHO LSI GIJUTSU KENKYU KUMIAI

International Classes:

H01L29/78; H01L29/423; H01L29/43; H01L29/49; (IPC1-7): H01L29/62; H01L29/78

Previous Patent: JPS56118369

Next Patent: JPS56118371