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Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS5679467
Kind Code:
A
Abstract:

PURPOSE: To obtain an MOS dynamic RAM powerful in resisting a soft error by using an N layer of a p-n junction positively as an area giving a negative threshold value.

CONSTITUTION: Ion is injected through a gate oxide film 3 of a P type Si substrate 1 to form a P+ layer 4. And then, an N layer 5 is formed and the end arpt A is extended to the external direction of the layer 4 by a sum or more of the deflection of a mask matching and the diffusion depth difference. Next, a poly Si gate electrode 6 is selectively formed and the end part A of the N layer 5 is placed to the outside direction by a dimension C. Therefore, the substrate 1 opposed to the electrode 6 is entirely negative in a threshold value in the N layer 5. Therefore, both a read out voltage and a critical charge quantity of error generation due to particles of a package material become high. Thereafter, An SiO2 film 7, a poly Si electrode 8 and an N type bit line 9 are installed as specified, thus, completing an MOS dynamic RAM.


Inventors:
YOSHIHARA TSUTOMU
Application Number:
JP15651879A
Publication Date:
June 30, 1981
Filing Date:
November 30, 1979
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
H01L27/10; H01L21/8242; H01L27/108; H01L29/78; H01L29/92; (IPC1-7): H01L27/10; H01L29/78; H01L29/94



 
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