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Patent Searching and Data


Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS58142580
Kind Code:
A
Abstract:

PURPOSE: To realize wide band and low noise semiconductor device by providing the P- layer between the P+ substrate and the N layer of the N channel junction type FET and by providing the P+ buried layer to the P- layer just below the gate.

CONSTITUTION: In an N channel junction type FET, an epitaxial N layer 2 is formed on a P+ type Si substrate 1 through a P- layer 6 and a gate is formed by forming a P+ region 4 at a part of the surface of layer 2. A P+ buried layer 7 is provided at a part of the layer 6 just below the region 4. According to this structure, a junction type FET having a low input and output capacitance can be obtained without changing a gate width/gate length, and accordingly without lowering a mutual conductance. It is because a depletion layer can be extended, at the time of applying a gate voltage, longer than that of the P+-N junction structure in both surfaces of junction by forming the P--N junction through the layer 6 provided between the N layer and P+ substrate and therefore a junction capacitance can be as much reduced. Therefore, a wide band and low noise junction type FET can be obtained.


Inventors:
TAIRA YASUO
Application Number:
JP2441782A
Publication Date:
August 24, 1983
Filing Date:
February 19, 1982
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H01L21/337; H01L29/80; H01L29/808; (IPC1-7): H01L29/80
Attorney, Agent or Firm:
Katsuo Ogawa (1 person outside)