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Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS58182861
Kind Code:
A
Abstract:

PURPOSE: To effectively prevent the electrostatic damage of an insulating gate in an IC, LSI formed of complementary insulated gate field effect transistor by forming deeply from the resistance region in the second conductive type semiconductor region.

CONSTITUTION: B ions are implanted with an oxidized film 8 formed on the surface of an N type substrate 1 as a mask, thereby forming P type wells 3, 5. P+ type diffused region 2 is formed to partly superpose at least with the P type well, and an N+ type diffused region 4 is formed on the surface of the P type well 3. A contact photoetching is performed for the oxidized film on the surface, and A electrodes 7a, 7b to become both terminals of P+ type diffused resistance, Al electrode 7c to become upper electrode of an N+P junction diode, and A wiring to connect between the electrodes are formed. The P-N junction surface with the substrate 1 is extended toward the depth direction of the substrate, and the radius of curvature is increased, and the withstand voltage due to concentration of the electric field does not decrease.


Inventors:
HOUYA KAZUO
MATSUDA TOSHIHIRO
Application Number:
JP6534782A
Publication Date:
October 25, 1983
Filing Date:
April 21, 1982
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H01L29/78; H01L27/02; H01L27/06; (IPC1-7): H01L27/08; H01L29/78
Domestic Patent References:
JPS5392675A1978-08-14
JPS5582467A1980-06-21
Attorney, Agent or Firm:
Katsuo Ogawa (1 person outside)



 
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