Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS59147447
Kind Code:
A
Abstract:
PURPOSE:To form a through-hole easily while preventing the disconnection of a wiring layer on the upper side by forming an inter-layer insulating layer in two layer structure, using a plasma silicon nitride as a lower layer and a sputtering silicon oxide as an upper layer to make etching rates differ and making the film thickness of the lower layer the same as the quantity of variance of the film thickness of the upper layer when wiring layers are laminated in the vertical direction while holding the insulating layer. CONSTITUTION:An insulating film 12 is formed on a semiconductor substrate 11, a lower layer Al wiring layer 13 of a predetermined pattern is formed on the film 12, and the whole surface is coated with an inter-layer insulating layer 14. The layer 14 is formed in two layer structure at that time, a lower layer 18 is formed from SiO2 in thickness of approximately 0.5mum through a plasma CVD method, and an upper layer 19 is formed from Si3N4 in thickness of approximately 1.0mum through a plasma method. Consequently, the layer 18 is made approximately the same as the variance of the thickness of the layer 19 while etching rates are made differ. Through-holes 16a and 16b are bored made correspond to the layers 13 through a normal method, and a second Al wiring layer 15 is applied on the through-holes while being brought into contact with the layers 13.
Inventors:
TAKAHASHI TAKAHIKO
OOWADA NOBUO
SATOU TOSHIHIKO
KURODA SHIGEO
YAMASHITA MICHIO
OOWADA NOBUO
SATOU TOSHIHIKO
KURODA SHIGEO
YAMASHITA MICHIO
Application Number:
JP2159083A
Publication Date:
August 23, 1984
Filing Date:
February 14, 1983
Export Citation:
Assignee:
HITACHI LTD
HITACHI MICROCUMPUTER ENG
HITACHI MICROCUMPUTER ENG
International Classes:
H01L21/3213; H01L21/302; H01L21/306; (IPC1-7): H01L21/302; H01L21/306
Attorney, Agent or Firm:
Akio Takahashi