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Patent Searching and Data


Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS59231866
Kind Code:
A
Abstract:

PURPOSE: To inhibit a parasitic bipolar effect, and to avoid the lowering of dielectric resistance by previously making the thickness of an inter-layer insulating film between an electrode wiring for an N type diffusion layer and a gate electrode thicker than that of an inter-layer insulating film in a region, in which there is no gate electrode, in an N channel MOS type transistor.

CONSTITUTION: N+ type source regions 2 and drain region 3 are diffused and formed to the surface layer section of a P type Si substrate 1 as a base region, and a shallow N+ type region 4 is formed to the surface section of the region 3 while being projected to both sides. The whole surface is coated with a thin gate insulating film, gate electrodes 5 are attached on channel regions 12 positioned among the regions 2 and 4, the whole surface is coated with an inter-layer insulating film 13, an opening is bored and a drain wiring 11 being in contact with the region 4 is applied, and the whole surface is coated with a protective film 14. In the constitution, an SiO2 film 15 thicker than the film 13 is added and interposed between the film 13 and the wiring 11 positioned on the electrode 5, the potential of the wiring 11 passing on the channel region 12 is weakened, and a parasitic bipolar effect is reduced.


Inventors:
TAKENAKA KAZUHIRO
Application Number:
JP10609183A
Publication Date:
December 26, 1984
Filing Date:
June 14, 1983
Export Citation:
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Assignee:
SUWA SEIKOSHA KK
International Classes:
H01L29/78; H01L21/768; H01L23/522; H01L29/06; (IPC1-7): H01L29/78
Attorney, Agent or Firm:
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