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Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS62125711
Kind Code:
A
Abstract:

PURPOSE: To form a peripheral circuit with a small occupied area by supplying a load current via a conduction channel type MISFET operated at a high current amplification factor without any back gate bias supplied.

CONSTITUTION: In outputting the 1st power voltage VPP fed to the input terminal 1 from an output terminal 3, a low voltage is fed to a MISFET Q3 from the 3rd signal terminal 6, the MISFET Q3 is conducted and the input terminal 1 and the output terminal 3 are conducted electrically. A high voltage boosted by a charge pump or the like from the 1st signal terminal 4 is fed to a MISFET Q1, which is conducted. A low voltage is fed to a MISFET Q3 from the 2nd signal terminal 5, the FET Q2 is conducted and a base electrode of the FET Q3 goes to a potential equal to the 1st power voltage VPP. Since the MISFET Q3 is of P-channel type, no back gate bias is fed and the FET Q3 is operated at a high current amplification factor, then the occupied area of the MISFET Q3 is very small.


Inventors:
OBATA HIROYUKI
Application Number:
JP26640885A
Publication Date:
June 08, 1987
Filing Date:
November 26, 1985
Export Citation:
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Assignee:
NEC CORP
International Classes:
H03K19/0175; H03K17/00; H03K17/687; H03K17/693; H03K19/00; H03K19/094; H03K19/0944; (IPC1-7): H03K17/687; H03K19/00; H03K19/094
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)



 
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